In this role you would have the following responsibilities: Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications. Support Senior Designers in their design and verification of complex circuit building blocks Identify and
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart
In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off. You will work in close interaction
Are you interested in working across various market segments (AI, Cloud, Networking, Storage…), designs, foundries and processes ranging from 3nm (and below) to 28nm (and above) to develop solutions for customer’s chip designs using the Synopsys IP
Senior Manager - System Architecture Team You will be leading a system architecture team tasked in developing =32Gbps NRZ and =112Gbps PAM4 serial-link transceivers. We are looking for a manager with theoretical knowledge and practical experience
We are looking for an experienced software developer to help build the Market-leading Software Security & Risk Management platform. You will work with a team of enthusiastic and dynamic software engineers, building a platform to help
Solutions Engineering, Staff Engineer Bengaluru, Karnataka India Apply Now Category: Engineering Hire Type: Employee Job ID 46034BR Date posted 10/13/2023 Hands on RTL2GDS. Complete PD block owner and closure. Tape Out experience, Debug and solve issues
You will be part of an excellent development team in System Level Design space involved in creation of Virtual Prototypes (simulation models) for SoCs/MCUs/ECUs and bring up of Linux/Android/AutoSar OS/Embedded SW applications, catering to early Software
Job Description: The selected candidate will be a technical leader of the Synopsys DesignWare Processor team in Hsinchu involving in development of leading edge DesignWare processor IP products such as HPC processors, NN accelerators, vision processors, as
As a ASIC Physical Implementation, Principal Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the
As a ASIC Physical Implementation, Sr Staff Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for
Design Verification Engineer Responsibilities Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM. Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification. Write test
Senior Physical Design Engineer The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide targeted
Analog and Mixed Signal Design Engineer, Staff Join us as an analog and mixed-signal design engineer in the PLL design team. Our designs enable the next generation of datacenters, automobiles and communications networks. You will work
Staff Design Engineer The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide targeted support
ASIC Architecture, Digital Design or Digital Verification Responsibilities Architecting, Designing and Verifying high speed mixed-signal PHYs like PCIe, Ethernet, USB Roles available in all these areas - working on new variants of these protocols. Key Requirements
Principal Digital Engineer Seeking a highly motivated and innovative experienced Digital Design Engineer with knowledge of ASIC development flow. The candidate will be working as part of a highly experienced mixed-signal design and verification team, targeting
Project Engineering Manager, Staff - High Speed Serdes IP Synopsys is looking for an adaptable, passionate, and resourceful Project Engineering Manager. A reputation for “getting the job done” and who is passionate, autonomous, and creative. A person
ASIC Physical Design Engineer, Senior The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers