Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are
Company:Qualcomm Canada ULCJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:Qualcomm is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team. The successful candidate will be responsible for developing and executing
Qualcomm Canada ULC seeks a Design Verification Engineer to join its memory subsystem verification team. You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic, and drive functional and code coverage closure. The candidate
Principal Physical Design Methodology Engineer Job ID 18396 Country Canada City Markham State/Province Markham Date Posted 15-Aug-2026 Job Category Job Subcategory Employee No Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader
Synopsys Inc. in Canada seeks a senior digital ASIC designer to own high-speed SerDes IP blocks and drive RTL design with clock-domain crossing and timing closure. You will partner with verification, DFT, and test teams to
Company Qualcomm Canada ULC Job Area Engineering Group, Engineering Group ASICS Engineering General Summary Qualcomm is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team. The successful candidate will be
Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are
Take on the role of Electrical Engineer specializing in Mixed Signal Design! Support SERDES PHY IP integration and enhance performance in CLIENT SoC applications. As an engineer in this position, you will be instrumental in both pre-silicon
Pay Rate: $(70 to 75)/hr T4 Support pre-silicon integration and post-silicon support of SERDES PHY IP. Support electrical analyses for power, signal, and clock integrity to ensure that SERDES IP operates successfully across many CLIENT SoC environments.