As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology
Become the Director of R&D Engineering at Synopsys in Ottawa, specializing in Ethernet SerDes and Interface PHY technologies. Your leadership will play a crucial role in AI and HPC advancements. In this senior leadership role, you will
Join Synopsys as a Senior Analog Design Engineer in Ottawa or Mississauga and drive advancements in high-performance analog products. Your deep knowledge in analog design will shape industry innovations. As a key member of our engineering team,
Elevate your career as a Lead ASIC Digital Design Engineer with Synopsys, specializing in innovative High Bandwidth Memory designs. Drive advancements in digital and mixed-signal technology in a collaborative environment. As part of our High Bandwidth Memory
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. Were a technology
Become a leader in R&D at Synopsys, specializing in AI SerDes solutions and high-speed protocol developments. Master the art of execution and team alignment in a dynamic environment. At Synopsys, were looking for an R&D Engineering Director who
Synopsys Inc in Ottawa is seeking a Senior Silicon Validation Engineer to lead bring-up and validation of next-gen memory interfaces. You will perform eye diagram analysis, run characterization across corners, and drive debug with lab instrumentation and
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
Senior Director R&D Engineering (Interface PHY / Ethernet SerDes) Job ID 18259 Country Canada City State/Province Ottawa (Hines Road) Date Posted 20-Jul-2026 Job Category Job Subcategory Employee No Descriptions & Requirements Job Description and Requirements We
Job ID 18341 Country Canada City Nepean State/Province Nepean Date Posted 05-Aug-2026 Job Category Job Subcategory Employee No Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to
A leading semiconductor company in Ottawa seeks an experienced engineering professional to manage global Silicon IP projects. The ideal candidate will have over 10 years of experience in semiconductor design, with a strong background in SOC,
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
Drive R&D Engineering excellence at Synopsys as a Senior Director, focusing on Ethernet SerDes and Interface PHY IP for transformative AI technologies. In this pivotal role, you will lead a distributed team dedicated to developing 112G and
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with
RTL/FPGA Design Engineer Project Duration: 12 Months + chances of further extension. Base pay range CA$110.00/hr - CA$135.00/hr Job Description Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering
We are open to hiring in Ottawa, ON and Mississauga, ON. We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence,
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with