Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has
Altera seeks a Static Timing Analysis Professional to advance FPGA design efforts in Toronto, Ontario. Your role will focus on executing timing analyses, resolving violations, and collaborating for optimal design outcomes. In this key position at Altera, you will leverage
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex
Join Altera as the Static Timing Analysis Manager in Toronto, Ontario, focusing on high-performance FPGA designs. Lead team dynamics while ensuring timing analysis excellence and optimization. This pivotal role requires a seasoned professional with a decade of experience in Static Timing Analysis. You will
General Information Job Title ASIC Physical Design, Sr Staff Engineer - 16724 Job ID 16724 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote
General Information Job Title ASIC Physical Design, Staff Engineer -16723 Job ID 16723 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote Eligible No
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: What we are doing has not been done. Shape the future of low power AI subsystems. Push the boundaries on features and performance. Qualcomm
The application window is expected to close on: 08/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group
What you’ll be doing: Drive Physical Design and timing analysis and closure of NVIDIA’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. Help in driving frontend and backend implementation including synthesis, equivalence
We are seeking a Senior Physical Design and Timing Engineer to work on high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block, cluster, and full‑chip levels. What you’ll be doing: Drive physical design and timing of
About the Role You have spent years deep in the signoff trenches, where timing closure is not theoretical and tape‑out deadlines are real. You know that the difference between a customer hitting their schedule and missing it
Drive customer success as a Senior Timing Signoff Engineer at Synopsys, specializing in complex timing challenges and signoff methodologies. Make a significant impact on customer tape-out projects. In this pivotal role, you will leverage 8 to 15 years
About the role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA,
Join Ciena as a Senior ASIC Engineer, focused on developing cutting‑edge Digital Signal Processing technology. Your expertise in synthesis and static timing will be pivotal for frontend implementation. As part of Ciena’s cutting‑edge team, you will have a
Become a vital part of Ciena as a Senior ASIC Engineer focusing on Digital Signal Processing technology. Your skills in synthesis and static timing will drive innovative ASIC designs. As part of Ciena’s advanced team, your work will
Elevate automotive communication as a Senior ASIC Design Engineer in a hybrid capacity in Toronto. Contribute to digital SoC design, verification, and advanced synthesis processes. This role targets seasoned engineers with over 10 years in ASIC
Join a pioneering team as a Senior ASIC Design Engineer in Toronto, focusing on digital SoC design within the automotive sector. Enjoy a hybrid work model while driving innovation. This role requires a seasoned engineer with
Company:Qualcomm Canada ULCJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to help create a
Embedded Systems Validation & Integration Engineer Are you passionate about building reliable, real-time embedded software that powers complex hardware systems in the real world? We’re looking for a hands‑on Embedded Systems Validation & Integration Engineer to
Qualcomm is seeking a skilled Camera Frontend Implementation Engineer to join their revolutionary engineering team in Canada. Contribute to the development and integration of state-of-the-art Camera IP for Snapdragon systems on chips. In this pivotal role,