Job Details: Job Description: Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs! This role will play a critical part in ensuring high-performance, power-efficient silicon by
Job Details: Job Description: Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross-functional teams to deliver high-performance, power-efficient designs.
Lead Alteras Static Timing Analysis team in Toronto, Ontario, ensuring the timing closure of advanced FPGA designs. Drive innovation and collaboration for high-performance, power-efficient silicon solutions. As a Static Timing Analysis Manager with over 10 years of expertise, you will guide a team
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex
Altera is looking for a Senior Static Timing Analysis Engineer to enhance FPGA designs in Toronto, Ontario. Focus on timing closure, debugging violations, and collaborating with cross-functional teams for optimal performance. In this pivotal role at Altera, you will perform
Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration
Our Mission Safety secures the software supply chain for the worlds data and development teams. We protect everywhere packages are actually used, from local developer machines to production environments, from traditional IDEs to AI coding assistants
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
Scope: Evertz is looking for a Junior FPGA Design Engineer to be part of Markham FPGA Design team responsible for developing video/audio processing, routing and transportation products. Responsibilities: Develop FPGA/MPSoC-based products Develop CPLD designs Design IP
About the Role You have spent years deep in the signoff trenches, where timing closure is not theoretical and tape‑out deadlines are real. You know that the difference between a customer hitting their schedule and missing it
Drive customer success as a Senior Timing Signoff Engineer at Synopsys, specializing in complex timing challenges and signoff methodologies. Make a significant impact on customer tape-out projects. In this pivotal role, you will leverage 8 to 15 years
Drive frontend ASIC implementation at Ciena, a leader in high-speed connectivity. This senior role emphasizes synthesis, static timing analysis, and logical equivalence checking. At Ciena, you will contribute to the Wavelogic Digital Signal Processor programs by executing frontend designs.
Elevate your career with Intel as a Senior Mixed Signal Design Engineer focusing on cutting-edge analog circuit design and verification in a hybrid work model. Youll specialize in static timing analysis and optimize mixed-signal systems. In this pivotal role,
Overview Our Arm Solutions Engineering SoC Security Team is seeking creative and enthusiastic SoC Design Engineers to join our diverse and highly-skilled team. We have exciting opportunities for innovative designers with demonstrated expertise in security design