Position Title: Acquisitions Officer II (Documentary Programming) Employment Type: Full-time Staff | Union Salary range: $80,125.52 - $87,918.29 Division: Media Reports To: Commissioning Editor, Documentaries Location: Toronto, Yonge & Eglinton (On-site) Reason for Vacancy: Existing Vacancy
Job Details: Job Description: Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs! This role will play a critical part in ensuring
Job Details: Job Description: Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with
Become a key part of our team as a Full-Time Real Estate Sign Installer in Edmonton. This role requires strong attention to detail and effective communication while working outdoors. We are seeking a reliable and hardworking
About Us: Headquartered in Ottawa, BTA Design serves the electronic design community from Canada, specializing in ASIC and FPGA design and verification, and embedded software development services. We augment and enhance our clients’ teams and accelerate
Please send your resume to: OverviewHashHub Inc. is an innovative semiconductor and IC design company focused on advanced chip solutions and high-performance computing technologies. We are expanding our backend design team and looking for passionate engineers
Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver
About the Position As a Digital Physical Design Engineer you will play a key role in backend implementation from netlist to GDSII on challenging blocks and sub‑systems. You will use advanced flows and techniques in single‑digit
Company Qualcomm Canada ULC Job Area Engineering Group ASICS Engineering General Summary Shape the future of low power AI subsystems. Push the boundaries on features and performance. Qualcomm Technologies Audio products are designed to offer premium
Drive customer success as a Senior Timing Signoff Engineer at Synopsys, specializing in complex timing challenges and signoff methodologies. Make a significant impact on customer tape-out projects. In this pivotal role, you will leverage 8 to
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely
About Us the company is an innovative semiconductor and IC design company focused on advanced chip solutions and high-performance computing technologies. We are expanding our backend design team and looking for passionate engineers — from new
Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group ASICS Engineering General Summary The successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoCs. We are looking
Company Qualcomm Canada ULC Job Area Engineering Group, Engineering Group ASICS Engineering General Summary What we are doing has not been done. Shape the future of low power AI subsystems. Push the boundaries on features and
About the Role You have spent years deep in the signoff trenches, where timing closure is not theoretical and tape‑out deadlines are real. You know that the difference between a customer hitting their schedule and missing
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely
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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification,
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing