General Information Job Title ASIC Physical Design, Sr Staff Engineer - 16724 Job ID 16724 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote
General Information Job Title ASIC Physical Design, Staff Engineer -16723 Job ID 16723 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote Eligible No
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: What we are doing has not been done. Shape the future of low power AI subsystems. Push the boundaries on features and performance. Qualcomm
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Our first-generation ASIC, Asimov, is a cutting-edge accelerator targeting frontier AI workloads, with
The application window is expected to close on: 08/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group
# Development Executive, Comedy; Scripted Content (English Services)Applylocations: Toronto, ONtime type: Full timeposted on: Posted Todaytime left to apply: End Date: July 21, 2026 (13 days left to apply)job requisition id: JR Position Title: Development Executive,
Drive customer success as a Senior Timing Signoff Engineer at Synopsys, specializing in complex timing challenges and signoff methodologies. Make a significant impact on customer tape-out projects. In this pivotal role, you will leverage 8 to
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
Senior Staff Applications Engineer - Timing Signoff Job ID 17319 Country Canada City State/Province British Columbia Date Posted 04-May-2026 Job Category Job Subcategory Applications Engineering Employee No Descriptions & Requirements Job Description and Requirements We Are
Join Altera as the Static Timing Analysis Manager in Toronto, Ontario, focusing on high-performance FPGA designs. Lead team dynamics while ensuring timing analysis excellence and optimization. This pivotal role requires a seasoned professional with a decade
Join Cisco’s innovative Common Hardware Group as an ASIC Physical Design Technical Leader, focusing on fullchip floorplans and cutting-edge design methodologies. Collaborate across teams to shape AI-era hardware solutions. With over 8 years of experience, you
The application window is expected to close on: 08/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
Explore the Senior Signoff Applications Engineer role at Synopsys in British Columbia, pivotal for customer success during tape-out. Apply your knowledge in timing analysis and tool usage. Be based in Vancouver or on the Canadian east
Join Synopsys as a Senior Staff ASIC Engineer specializing in Physical Design, where your innovation will shape next-generation chip technologies. Leverage your vast experience in SoC implementations and physical design flows. In this role, you will
Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group ASICS Engineering General Summary The successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoCs. We are looking
Overview At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
The application window is expected to close on: 08/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware
Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing