General Information Job Title Senior Staff Applications Engineer - Timing Signoff Job ID 17319 Country Canada City Vancouver State/Province British Columbia Date Posted 04-May-2026 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No
Altera seeks a Static Timing Analysis Professional to advance FPGA design efforts in Toronto, Ontario. Your role will focus on executing timing analyses, resolving violations, and collaborating for optimal design outcomes. In this key position at Altera, you will leverage
Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex
Join Altera as the Static Timing Analysis Manager in Toronto, Ontario, focusing on high-performance FPGA designs. Lead team dynamics while ensuring timing analysis excellence and optimization. This pivotal role requires a seasoned professional with a decade of experience in Static Timing Analysis. You will
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: The successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoCs. We are looking for individuals
General Information Job Title ASIC Physical Design, Sr Staff Engineer - 16724 Job ID 16724 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote
General Information Job Title ASIC Physical Design, Staff Engineer -16723 Job ID 16723 Country Canada City Nepean State/Province Nepean Date Posted 01-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote Eligible No
General Information Job Title Senior Applications Engineer Job ID 17691 Country Canada City Vancouver State/Province British Columbia Date Posted 01-Jun-2026 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible Yes Descriptions & Requirements
Company:Qualcomm Canada ULC Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: What we are doing has not been done. Shape the future of low power AI subsystems. Push the boundaries on features and performance. Qualcomm
Join Synopsys as an Expert Timing Signoff Engineer in British Columbia, making a direct impact on customer tape-out success. Your expertise in timing analysis will pave the way for innovation. This role, based in Vancouver or on Canadas east
About the Role You have spent years deep in the signoff trenches, where timing closure is not theoretical and tape‑out deadlines are real. You know that the difference between a customer hitting their schedule and missing it
Drive customer success as a Senior Timing Signoff Engineer at Synopsys, specializing in complex timing challenges and signoff methodologies. Make a significant impact on customer tape-out projects. In this pivotal role, you will leverage 8 to 15 years
Location: Ottawa, ON (on-site) Employment type: Full-time permanent Salary range: $130,000 – $165,000 CAD per year; competitive salaries will be negotiated commensurate with experience — this range is a guideline About Q-Block Computing: Q-Block Computing builds
Position Overview The Applications Engineer works directly with Siemens EDA customers to help grow the adoption and use of Siemens Solido software in their library characterization and verification flows. This position combines technical depth with strong
Please send your resume to: Overview HashHub Inc. is an innovative semiconductor and IC design company focused on advanced chip solutions and high-performance computing technologies. We are expanding our backend design team and looking for passionate
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology