Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has
Altera seeks a Static Timing Analysis Professional to advance FPGA design efforts in Toronto, Ontario. Your role will focus on executing timing analyses, resolving violations, and collaborating for optimal design outcomes. In this key position at Altera, you will leverage
Join Altera as the Static Timing Analysis Manager in Toronto, Ontario, focusing on high-performance FPGA designs. Lead team dynamics while ensuring timing analysis excellence and optimization. This pivotal role requires a seasoned professional with a decade of experience in Static Timing Analysis. You will
Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. The role will be critical in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex
About the role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA,
Join Ciena as a Senior ASIC Engineer, focused on developing cutting‑edge Digital Signal Processing technology. Your expertise in synthesis and static timing will be pivotal for frontend implementation. As part of Ciena’s cutting‑edge team, you will have a
Become a vital part of Ciena as a Senior ASIC Engineer focusing on Digital Signal Processing technology. Your skills in synthesis and static timing will drive innovative ASIC designs. As part of Ciena’s advanced team, your work will
Join a pioneering team as a Senior ASIC Design Engineer in Toronto, focusing on digital SoC design within the automotive sector. Enjoy a hybrid work model while driving innovation. This role requires a seasoned engineer with
Embedded Systems Validation & Integration Engineer Are you passionate about building reliable, real-time embedded software that powers complex hardware systems in the real world? We’re looking for a hands‑on Embedded Systems Validation & Integration Engineer to
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
Overview Huawei Canada has an immediate 6-8 month internship opening for an Engineer. About the team: Initially founded in 1991 as Huaweis ASIC Design Center, the IC Lab is a leading global fabless semiconductor lab. This
Join to apply for the Senior ASIC (Front End) Design Engineer role at Ethernovia Continue with Google Continue with Google Join to apply for the Senior ASIC (Front End) Design Engineer role at Ethernovia Get AI-powered
Overview At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
Location: Ottawa, ON (on-site) Employment type: Full-time permanent Salary range: $130,000 – $165,000 CAD per year; competitive salaries will be negotiated commensurate with experience — this range is a guideline About Q-Block Computing: Q-Block Computing builds
Stadium Vault is currently our primary focus. It’s a gamified sports and TCG collectibles commerce platform where fans rip packs, build collections, and compete for rare cards. Think sports cards x Whatnot x content-first commerce. We’ve
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology
Location: Ottawa, ON (on-site) Employment type: Full-time permanent Salary range: $130,000 – $165,000 CAD per year; competitive salaries will be negotiated commensurate with experience — this range is a guideline About Q-Block Computing: Q-Block Computing builds
Coherent RF Architect – Job Description We are seeking a hands‑on Coherent RF Architect to lead silicon bring‑up, validation, and production test development for a mixed‑signal Analog Front‑End (AFE) featuring high‑speed DACs, ADCs, PLL/clocking, and the